1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device structure, and more particularly, to an ESD protection device structure of a gate-grounded metal-oxide-semiconductor transistor.
2. Description of the Prior Art
Electrostatic discharge (ESD) usually occurs in semiconductor devices. The ESD phenomenon occurs when excess charges are transmitted from the input/output (I/O) pin to the integrated circuit too quickly, which damages the internal circuit. In order to solve such a problem, manufacturers normally build an ESD protection device between the internal circuit and the I/O pin. The ESD protection device is initiated before the ESD pulse enters the internal circuit for discharging the excess charges, and thus ESD-related damage is decreased.
Recently, in order to prevent the internal circuit from damage generated by ESD phenomenon, the prior-art ESD protection device uses a PMOS transistor and an NMOS transistor to protect the internal circuit. Generally, the discharge path of the ESD protection device includes four modes, such as a positive-to-VSS (PS) mode, a negative-to-VSS (NS) mode, a positive-to-VDD (PD) mode, and a negative-to-VDD (ND) mode. Under the PD and NS modes, the parasitic diodes at the PMOS transistor and the NMOS transistor are used to provide the ESD protection function. On the other hand, in the ND and PS modes, the parasitic bipolar transistors at the PMOS transistor and the NMOS transistor are used for protecting the internal circuit. However, the turned-on voltages of the parasitic bipolar transistors are high, and the gate oxide layer of the NMOS transistor or the PMOS transistor is becoming thinner with the continuing scaling-down of semiconductor integrated circuit (IC) device dimensions, thus the breakdown voltages of the gate oxide layer will become smaller, resulting in that the gate oxide layer easily burns out due to a high ESD current such that the prior-art ESD protection device loses its protection function.
As a result, how to provide an effective ESD protection device as the process scale and device spaces of ICs are continuously reduced is still one of the important issues to the manufacturers.